1. Field of the Invention
The present invention relates to a semiconductor device and its manufacturing method, further detailedly relates to technique for integrating various type of MOS transistors composing a driver for driving a liquid crystal for example on one semiconductor substrate.
2. Description of the Related Art
Referring to the drawings, a conventional type semiconductor device and its manufacturing method will be described below. The driver for driving a liquid crystal described above is composed of an N-channel MOS transistor and a P-channel MOS transistor which are respectively a logic device of 3 V for example, an N-channel MOS transistor and a P-channel MOS transistor respectively of 30 V for example which respectively have high resistance to voltage, an N-channel double-diffused (D) MOS transistor and a P-channel DMOS transistor and an N-channel MOS transistor of 30 V for example for a level shifter and others.
As for the DMOS transistor structure described above, impurities different in a conductive type are diffused into a diffused layer formed on the side of the main surface of a semiconductor substrate so as to form a new diffused layer, difference in diffusion in the lateral direction of these diffused layers is utilized for effective channel length and a short channel is formed to be a device in which on-state resistance is reduced.
FIG. 14 is a sectional view for explaining a conventional type MOS transistor and shows the structure of an N-channel DMOS transistor as an example. The description of the structure of a P-channel MOS transistor is omitted, however, it is well-known that a P-channel MOS transistor is different only in a conductive type from an N-channel MOS transistor and has the similar structure.
As shown in FIG. 14, a reference numeral 51 denotes a semiconductor substrate of one conductive type, for example a P type, 52 denotes an N-type well, a P-type body layer 53 is formed in the N-type well 52, an N-type diffused layer 54 is formed in the P-type body layer 53 and an N-type diffused layer 55 is formed in the N-type well 52. A gate electrode 57 is formed on the surface of the substrate via a gate oxide film 56 and a channel layer 58 is formed in the superficial area of the P-type body layer 53 immediately under the gate electrode 57.
The N-type diffused layer 54 functions as a source diffused layer, the N-type diffused layer 55 functions as a drain diffused layer and the N-type well 52 under an oxide film 59 according to LOCOS method functions as a drift layer. Reference numerals 60 and 61 respectively denote a source electrode and a drain electrode, 62 denotes a P-type diffused layer for acquiring the electric potential of the P-type body layer 53 and 63 denotes a layer insulating film.
In the DMOS transistor described above, the concentration on the surface of the N-type well 52 is enhanced by diffusing impurities into it, as a result, current easily flows on the surface of the N-type well 52 and resistance to voltage can be enhanced.
The DMOS transistor having such structure is called surface relaxation-type ((REduced SURface Field: RESURF) DMOS and the concentration of dopants in the drift layer of the N-type well 52 is set so that it meets a condition of RESURF. Such technique is disclosed in JP-A-9-0.139438 and others.
In the DMOS transistor described above is formed, high temperature heat treatment for forming the P-type body layer 53 is required after a gate electrode is formed, therefore, as the concentration in a profile ruled every 0.35 μm for example in a microdevice operated at low voltage gets out of order, a micro MOS transistor starts to be formed in the present circumstances after a gate electrode of a DMOS transistor is formed and high temperature heat treatment for forming a P-type body layer is finished and there is a problem that a manufacturing process is extended.
As the gate length of the DMOS transistor is basically determined by diffusion coefficients by different ions and a diffusion started position, there is also a problem that the degree of the freedom in design of gate length is small.